14.25 CP0 Instructions
Branch on Coprocessor 0
On the R4400 processor, CacheOps that hit in the specified cache set the CH bit in the Diagnostic field of the CP0 Status register (bit 18). Though it was undocumented, this bit could be tested by the Branch on Coprocessor 0 instructions (bc0t, bc0f, bc0tl, bc0fl).
The R10000 processor also implements the CH bit but it is not associated with a Coprocessor 0 condition. Instead, execution of a branch on Coprocessor 0 instruction takes a Reserved Instruction exception.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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